1 ps8442a 08/06/01 product description pericom semiconductor?s pi74avc + series of logic circuits are produced using the company?s advanced submicron cmos technology, achieving industry leading speed. the pi74avc+16345 is ideal for driving memory modules in systems where multiple memory modules are used. one each of the four output banks drive a different module; modules can be added or removed without affecting the signal integrity of the other modules in the system. dual clock enables (cex) allow use of the device in high-speed memory interleaving applications where the clock can be alternately enabled and disabled, allowing the address to be held for additional cycles during memory access. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2.5v, registered 1-bit to 4-bit address driver w/3-state outputs logic block diagram product features ? pi74avc + 16345 is designed for low-voltage operation, v cc = 1.65v to 3.6v ? true 24ma balanced drive @3.3v ? i off supports partial power down operation ? i/o tolerant to 3.6v ? all outputs contain a patented ddc (dynamic drivecontrol) circuit that reduces noise without degrading propagation delay. ? industrial operation: ?40c to +85c ? available packages: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k) ce1 d1 1q1 d2 4q1 1q2 4q2 d3 1q3 d4 4q3 1q4 4q4 1 oe 29 8 14 15 21 clk 28 ce d ce d ce d ce d ce2 d5 1q5 d6 4q5 1q6 4q6 d7 1q7 d8 4q7 1q8 4q8 56 36 42 43 49 ce d ce d ce d ce d pi74avc + 16345
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 2 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s t u p n is t u p t u o x e ce ok l cx dx q x hl x x 0 b xl l x 0 b ll - ll ll - hh xh x x z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 ce1 1q1 2q1 gnd 3q1 4q1 v cc d1 1q2 2q2 gnd 3q2 4q2 d2 d3 1q3 2q3 gnd 3q3 4q3 d4 v cc 1q4 2q4 gnd 3q4 4q4 clk ce2 1q8 2q8 gnd 3q8 4q8 v cc d8 1q7 2q7 gnd 3q7 4q7 d7 d6 1q6 2q6 gnd 3q6 4q6 d5 v cc 1q5 2q5 gnd 3q5 4q5 oe pin description truth table (1) note: 1. h = high signal level l = low signal level x = irrelevant z = high impedance - = low-to-high transition b0 = previous state pin configuration 56-pin a, k e m a n n i pn o i t p i r c s e d e o) w o l e v i t c a ( s t u p n i e l b a n e t u p t u o e t a t s - 3 k l ct u p n i k c o l c e c x ) w o l e v i t c a ( s t u p n i e l b a n e k c o l c d x s t u p n i a t a d x q x s t u p t u o e t a t s - 3 d n gd n u o r g v cc r e w o p
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 3 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 recommended operating conditions (1) notes: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation. . n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o 5 6 . 16 . 3 v y l n o n o i t n e t e r a t a d 2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i hv c c v 2 . 1 =v c c v c c v 5 9 . 1 o t v 5 6 . 1 = x 5 6 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 = 2 v l i e g a t l o v t u p n i l e v e l - w o lv c c v 2 . 1 =d n g v c c v 5 9 . 1 o t v 5 6 . 1 = x 5 3 . 0v c c v c c v 7 . 2 o t v 3 . 2 = 7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u oe t a t s e v i t c a0v c c e t a t s - 3 06 . 3 i h o t n e r r u c t u p t u o l e v e l - h g i hv c c v 5 9 . 1 o t v 5 6 . 1 =6 ? a m v c c v 7 . 2 o t v 3 . 2 = 2 1 ? v c c v 6 . 3 o t v 3 =4 2 ? i l o t n e r r u c t u p t u o l e v e l - w o l v c c v 5 9 . 1 o t v 5 6 . 1 = 6 v c c v 7 . 2 o t v 3 . 2 = 2 1 v c c v 6 . 3 o t v 3 =4 2 d t d e t a r l l a f r o e s i r n o i t i s n a r t t u p n i vv c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o 0 4 ?5 8c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc .................................................... ?0.5v to +4.6v input voltage range, v i ............................................................ ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) .................... ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) ............................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ............................................. ?50ma output clamp current, i ok (v o <0) ....................................... ?50ma continuous output current, i o ............................................................. 50ma continuous current through each v cc or gnd .................. 100ma package thermal impedance, q ja (3) : package a .................... 64c/w package k .................... 48c/w storage temperature range, t stg ....................................... ?65c to 150c notes: 1.input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2.output positive-voltage rating may be exceeded up to 4.6v maximum if theoutput current rating is observed. 3.the package thermal impedance is calculated in accordance with jesd 51.
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 4 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e t ) 1 ( v c c . n i m. p y t. x a ms t i n u v h o i h o 0 0 1 ? = m av 6 . 3 o t v 5 6 . 1v c c v 2 . 0 ? v i h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i l o 0 0 1 = m av 6 . 3 o t v 5 6 . 12 . 0 i l o 6 =m v a h i v 7 5 . 0 =v 5 6 . 15 4 . 0 i l o 2 1 =m v a h i v 7 . 0 =v 3 . 25 5 . 0 i l o 4 2 =m v a h i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 m a i f f o v i v r o o v 6 . 3 =0 0 1 i z o v i v = c c d n g r ov 6 . 30 1 i c c v o v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o c v i v = c c d n g r o v 5 . 24 f p v 3 . 34 s t u p n i a t a d v 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r o v 5 . 28 v 3 . 38 note: 1. typical values are measured at t a = 25c. dc electrical characteristics (over the operating range, t a = ?40 c + 85 c)
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 5 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u n i mx a mn i mx a mn i mx a mn i mx a mn i mx a m f k c o l c y c n e u q e r f k c o l c 0 5 10 8 10 8 1z h m t w w o l r o h g i h k l c , h t d i w e s l u p0 . 633 s n t u s w o l r o h g i h , k l c o t x e c , e m i t p u t e s0 . 25 . 15 . 1 t u s w o l r o h g i h , k l c o t x d , e m i t p u t e s0 . 25 . 15 . 1 t h w o l r o h g i h , k l c o t x e c , e m i t d l o h000 t h w o l r o h g i h , x d o t k l c , e m i t d l o h5 . 05 . 05 . 0 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 5 10 8 1?0 8 1? s n t d p k l cx q x5 . 4? 1 . 3?7 . 2 t n e e ox q x3 . 5? 5 . 4?9 . 3 t s i d e ox q x6 . 5? 6 . 3?4 . 3 t ) o ( k s w e k s t u p t u o ) 1 ( 5 . 0? 5 . 0?5 . 0 t ) b ( k s w e k s t u p t u o ) 1 ( 3 . 0? 3 . 0?3 . 0 switching characteristics (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) operating characteristics, t a = 25 c s r e t e m a r a ps n o i t i d n o c t s e t v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e t u p t u o c l z h m 0 1 = f , f p 0 = g n i h c t i w s s t u p t u o r u o f 4 85 90 1 1 f p d e l b a s i d s t u p t u o8 45 53 6 note: 1. this is the skew between any two outputs of the same package, and switching in the same direction. for t sk(o) output 1 and output 2 are any two outputs. for t sk(b) output 1 and output 2 are in the same bank. timing requirements (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4)
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 6 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 7 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k w 1 k w 0.15v 0.15v 30
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 8 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 30
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 9 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 0.3v 0.3v 30
pi74avc+16345 2.5v, registered 1-bit to 4-bit address driver with 3-state outputs 10 ps8442a 08/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56-pin tssop (a) package 56-pin tvsop (k) package .002 .006 seating plane .007 .011 .004 .008 1 56 .236 .244 0.50 0.17 0.27 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 max. 1.20 6.0 6.2 .547 .555 13.9 14.1 .319 8.1 .0197 bsc bsc .047 .031 .041 seating plane .016 bsc 1 56 .169 .177 11.20 11.40 4.30 4.50 1.20 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 6.4 .252 bsc .005 .009 .441 .449 max. ordering information a t a d g n i r e d r on o i t p i r c s e d a 5 4 3 6 1 + c v a 4 7 i p p o s s t c i t s a l p e d i w l i m - 0 4 2 , n i p - 6 5 k 5 4 3 6 1 + c v a 4 7 i p p o s v t c i t s a l p e d i w l i m - 3 7 1 , n i p - 6 5
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